Generally, semiconductor memory devices are divided into volatile memories and nonvolatile memories. The volatile memories, including chiefly random access memories (RAM) such as dynamic random access memories (DRAM) and static random access memories (SRM), retain their memory data when power is turned on, but lose the stored data when the power is turned off. In contrast, the nonvolatile memories, including chiefly read only memories (ROM), retain their memory data even after the power is turned off.
The nonvolatile memories may be subdivided into ROM, programmable ROM (PROM), erasable PROM (EPROM), and electrically erasable PROM (EEPROM).
From the view point of process technology, the nonvolatile memories may be divided into a floating gate family and a metal insulator semiconductor (MIS) family comprising a multi-layer of two or more dielectrics. The memory devices of the floating gate family use potential wells to achieve memory characteristics. For instance, EPROM tunnel oxide (ETOX) structure and split gate structure are widely applied to flash EEPROM. The split gate structure comprises two transistors in one cell. On the other hand, the memory devices of the MIS family perform memory functions by using traps positioned on a bulk dielectric, the interface between dielectrics, and the interface between the dielectric and the semiconductor. At present, the MONOS (metal oxide nitride oxide semiconductor)/SONOS (semiconductor oxide nitride oxide semiconductor) structure is chiefly being employed for the flash EEPROM.
FIG. 1 is a cross-sectional view of a flash memory cell structure formed by a conventional technology. Referring to FIG. 1, a gate oxide layer 12 is deposited on a semiconductor substrate 10 having at least one device isolation layer 11. A first polysilicon layer 13 is deposited on the gate oxide layer 12. The first polysilicon layer 13 is used as a floating gate. A dielectric layer 15 and a second polysilicon layer 16 are sequentially deposited on the first polysilicon layer 13. The second polysilicon layer 16 is used as a control gate. A metal layer 17 and a nitride layer 18 are sequentially deposited on the second polysilicon layer 16. Next, some portion of the gate oxide layer 12, the first polysilicon layer 13, the dielectric layer 15, the second polysilicon layer 16, the metal layer 17, and the nitride layer 18 are removed in cell structure to complete a flash memory cell.
The above-mentioned flash memory cell has a floating gate and a control gate of flat-plate type. Generally, in a flash memory, electric potential of a control gate has to be thoroughly transferred into a floating gate to enhance the erase and program characteristics of a device. For example, when a flash memory performs the program function using hot carriers, the voltages of 0 V, 5 V, and 9V are applied to a source, a drain, and a control gate, respectively. Here, if the voltage applied to the control gate is thoroughly transferred to a gate oxide via a floating gate and forms an electric field, hot electrons are more rapidly injected into the floating gate. Contrarily, when the flash memory performs the erase function, the voltages of −7 V and 5 V are applied to the control gate and the source, respectively. In this case, electrons in the floating gate move toward the source by Fowler-Nordheim (F-N) tunneling. Here, if the capacitance between the control gate and the floating gate is high and the capacitance between the floating gate and a substrate is low, the voltage of the floating gate is maintained at a very low value and, therefore, the more electrons move toward the source to increase the erase speed. In conclusion, in performing the program or erase function, the smaller the voltage difference between the floating gate and the control gate becomes, the faster the operation speed of the flash memory becomes.
To improve the program and erase characteristics of a semiconductor device, a method of using a material with high dielectric constant as a dielectric layer between the floating gate and the control gate has been suggested. However, the suggested method is in progress at present and requires more technical development.
In order to improve the program and erase characteristics of a semiconductor device, other methods of increasing the capacitance by enlarging the surface area between the control gate and the floating gate are put to practical use. For example, an OSC (One Cylinder Storage) structure or a DCS (Double Cylinder Storage) structure is employed to increase the capacitance of capacitors. However, such prior arts require complicated fabrication processes and have a difficulty in maintaining constant capacitance as the level of integration degrees changes. In addition, as the floating gate three-dimensionally is completed, the large surface area between the floating gate and the substrate may degrade the program and erase characteristics of a semiconductor device. Thus, a method for fabricating a structure is required which can increase the area between the control gate and the floating gate without changing the area between the floating gate and the substrate.
Korean Patent Publication No. 2002-96747 discloses a flash memory fabrication method. In particular, the method increase the area between a control gate and a floating gate by placing an embossed layer made of HSG (Hemisphere Shaped Grains) therebetween, therefore maximizing the capacitance.
PCT Publication No. WO245,175 discloses another flash memory fabrication method. In particular, the method places a convex-concave shaped layer after deposition of amorphous polysilion on a substrate through a CVD (Chemical Vapor Deposition) process, thereby increasing a coupling ratio.
However, such methods for forming the embossed layer made of HSG and the convex-concave shaped layer require additional processes such as a deglaze process and, therefore, the fabrication processes become complicated.